Method of fabricating semiconductor device

ABSTRACT

Provided is a method of fabricating a semiconductor device including a dual silicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.

PRIORITY STATEMENT

This application claims priority under U.S.C. §119 to Korean PatentApplication No. 10-2008-0042452, filed on May 7, 2008, in the KoreanIntellectual Property Office (KIPO), the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field

Example embodiments relate to a method of fabricating a semiconductordevice, and more particularly, to a method of fabricating asemiconductor device, including applying both a dual silicide processand a dual stress process.

2. Description of the Related Art

As semiconductor devices become more highly integrated, the line widthof transistor gate electrodes becomes narrower, thereby increasingresistance of the gate electrodes. Also, as transistor source/drainjunctions become thinner, gate electrode resistance increases. In orderto increase the operating speed of semiconductor devices, reducing theirresistance is beneficial. In order to reduce resistance of a gateelectrode, the gate electrode is formed of a polysilicon layer and arefractory metal silicide layer. Also, in order to reduce resistance ofa source/drain region, a refractory metal silicide layer is formed onthe source/drain region. For this, a refractory metal is deposited on apolysilicon gate electrode and a source/drain region, and then asilicide is simultaneously formed on both the gate electrode and thesource/drain region.

However, when a silicide is formed, thicknesses of silicides of asource/drain region and a gate region of an NMOS region and a PMOSregion vary depending on the structures of an active region and apolysilicon gate electrode of the NMOS region and the PMOS region. Thus,resistance Rs varies in the NMOS region and the PMOS region. Also, asilicide may grow in an edge portion of the active region according tothe shape of the edge portion of a device isolation layer, and thesilicide may cause junction leakage. Because the shape of the edgeportion of the device isolation layer in the PMOS region and the NMOSregion may vary, excessive growth of the silicide may occur in anyregion of the PMOS region and the NMOS region. Also, excessively grownsilicide may affect resistance Rs of the silicide when criticaldimensions (CDs) of an active region and a gate electrode are relativelysmall, while insignificantly affecting resistance Rs when CDs thereofare relatively large. Thus, the resistance Rs varies depending on theCDs. In order to overcome this problem, a dual silicide process fordifferently forming a silicide in an NMOS region and a PMOS region maybe used.

Furthermore, after the dual silicide process, a stress is applied to afield effect transistor (FET), characteristics of the FET may beimproved. A tensile stress increases electron mobility, and acompressive stress increases hole mobility. Accordingly, a tensilestress is applied to a channel of a transistor of an NMOS region toincrease electron mobility, thereby increasing drain current of anN-type transistor. Also, a compressive stress is applied to a channel ofa transistor of an PMOS region to increase hole mobility, therebyincreasing drain current of a P-type transistor.

SUMMARY

The present invention relates to a method of fabricating a semiconductordevice including a dual silicide process.

According to one example embodiment, a method of fabricating asemiconductor device may include sequentially siliciding and stressing afirst MOS region, and sequentially siliciding and stressing a second MOSregion after siliciding and stressing the first MOS region, the secondMOS region being a different type than the first MOS region.

The sequentially siliciding and stressing the first MOS region includesforming a silicide protection layer in the second MOS region, silicidingthe first MOS region, and stressing the first MOS region. Stressing thefirst MOS region includes forming a first stress liner over the firstMOS region. The sequentially siliciding and stressing the second MOSregion includes siliciding the second MOS region using the first stressliner to protect the first MOS region from being silicided, andstressing the second MOS region.

The first MOS region is exposed and a silicide blocking layer is formedin the second MOS region. First metal silicides are formed on the gateelectrode and the source/drain region of the exposed first MOS region,and the silicide protection layer is removed. The second MOS region isexposed and a first stress liner is formed in the first MOS region wherethe first metal silicides are formed. Second metal silicides are formedon the gate electrode and the source/drain region of the exposed secondMOS region, and a second stress liner is formed in the second MOS regionwhere the second metal silicides are formed.

The first MOS region may be an NMOS region, and the second MOS regionmay be a PMOS region. Stressing the first MOS region may includeapplying a compressive stress, and stressing the second MOS region mayinclude applying a tensile stress. The first MOS region may be a PMOSregion, and the second MOS region may be an NMOS region. Stressing thefirst MOS region may include applying a tensile stress, and stressingthe second MOS region may include applying a compressive stress. Thesilicide protection layer, the first stress liner and the second stressliner may be formed of SiCN, Si₃N₄, SiON, SiBN, SiO₂, SiC, SiC:H orSiCOH. Each of the first stress liner and the second stress liner may beformed to have a thickness in the range of about 10 Å to about 1,000 Å.The gate electrode may include conductive polysilicon.

Forming the first metal silicides may include forming a first metallayer on the semiconductor substrate and the gate electrode in the firstMOS region, and on the silicide protection layer in the second MOSregion; forming the first metal silicides on the gate electrode and thesource/drain region of the first MOS region by performing a heattreatment process on the portion of the semiconductor substrate wherethe first metal layer is formed; and removing the first metal layerformed on the silicide protection layer in the second MOS region. Thefirst metal layer may include Ti, Co, Ni, V, Er, Zr, Hf, Mo or Yb, andthe first metal layer may further include Pt, V or Sn.

Forming the second metal silicides may include forming a second metallayer on the first stress liner in the first MOS region and on thesemiconductor substrate and the gate electrode in the second MOS region;forming the second metal silicides on the gate electrode and thesource/drain region of the second MOS region by performing a heattreatment process on the portion of the semiconductor substrate wherethe second metal layer is formed; and removing the second metal layerformed on the silicide protection layer in the first MOS region. Thesecond metal layer may include Ti, Co, Ni, Pt, Ir or Pd. The secondmetal layer may further include Pt, V or Sn.

Thin film deposition, photolithography, and etching processes should berepeatedly performed in order to apply both a dual silicide process anda dual stress process, thereby increasing manufacturing costs and time.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. FIGS. 1A-1J represent non-limiting, example embodiments asdescribed herein.

FIGS. 1A through 1J are cross-sectional views for explaining a method offabricating a semiconductor device, according to example embodiments.

It should be noted that these Figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which example embodiments are shown.Example embodiments may, however, be embodied in many different forms,and should not be construed as being limited to the embodiments setforth herein; rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey theconcept of example embodiments to those skilled in the art. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity. Like reference numerals denote like elements throughout thespecification.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofexample embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIGS. 1A-1J are cross-sectional views for explaining a method offabricating a semiconductor device, according to example embodiments.Referring to FIG. 1A, a device isolation layer 102 may be formed in asemiconductor substrate 100 to define an active region. The activeregion may be divided into an NMOS region (NFET region) where an nchannel MOSFET is formed and a PMOS region (PFET region) where a pchannel MOSFET is formed. Gate electrodes 110 may be formed in the NMOSregion and the PMOS region to form source/drain regions 104 andsource/drain regions 106, respectively. Each of the gate electrodes 110may include a gate insulating layer 111 as well as a conductivepolysilicon 113, an offset oxide layer 115, and a spacer 117 that areformed on the gate insulating layer 111. The offset oxide layer 115 andthe spacer 117 may be formed of a silicon oxide and a silicon nitride,respectively. The gate electrodes 110 may be dual gate electrodeswhereby the gate electrode in the NMOS region has a conductivityopposite to that in the PMOS region.

Referring to FIG. 1B, after a silicide protection layer 122 is formed onthe entire surface of the semiconductor substrate 100, the portion ofthe silicide protection layer 122 in the NMOS region is removed using aphotographic etching process so as to expose only the NMOS region. Thesilicide protection layer 122 may be formed of SiCN, Si₃N₄, SiON, SiBN,SiO₂, SiC, SiC:H or SiCOH. The silicide protection layer 122 may beremoved by dry etching or wet etching.

Referring to FIG. 1C, a first metal layer 132 is formed on the entirestructure, for example, on the semiconductor substrate 100 and the gateelectrode 110 in the NMOS region, and on the portion of the silicideprotection layer 122 in the PMOS region. The first metal layer 132 mayinclude Ti, Co or Ni, and may further include Pt, V, or Sn. Also, thefirst metal layer 132 may include V, Er, Zr, Hf, Mo or Yb, and mayfurther include Pt, V, or Sn. The Pt, V, or Sn may function to increasethermal stability when performing a silicidation reaction. A cappinglayer (not shown) may be optionally formed on the first metal layer 132.The capping layer helps maintain thermal stability and helps prevent orreduce oxidization of the first metal layer 132 when performing asilicidation reaction.

Referring to FIG. 1D, metal silicides 108 and 118 may be formed on thesource/drain region 104 and the gate electrode 110 of the NMOS regionthrough a silicidation reaction by performing a heat treatment processon the semiconductor substrate where the first metal layer 132 isformed. The metal silicides 108 and 118 may be formed of TiSi₂, CoSi₂,NiSi, VSi₂, ErSi, ZrSi₂, HfSi, MoSi₂, CrSi or YbSi. The metal silicides108 and 118 may include Pt, V, or Sn. In the PMOS region, because thefirst metal layer 132 is formed on the silicide protection layer 122, ametal silicide may not be formed in the PMOS region.

Referring to FIG. 1E, the first metal layer 132 remaining after thesilicidation reaction is performed may be removed, and then the portionof the silicide protection layer 122 in the PMOS region may be removed.In the NMOS region, the source/drain region 104 and the gate electrode110 where the metal silicides 108 and 118 are formed thereon may beexposed. On the other hand, in the PMOS region, the gate electrode 110and the source/drain region 106 where a metal silicide is not formedthereon are exposed.

Referring to FIG. 1F, after a first stress liner 124 is formed on theentire structure, the portion of the first stress liner 124 in the PMOSregion may be removed, and only the portion of the first stress liner124 in the NMOS region remains. The first stress liner 124 may be formedso as to apply a compressive stress, and may be formed of SiCN, Si₃N₄,SiON, SiBN, SiO₂, SiC, SiC:H or SiCOH, similar to the silicideprotection layer 122. The first stress liner 124 may be formed to have athickness in the range of about 10 Å to about 1,000 Å. The first stressliner 124 may increase electron mobility in an N channel by applying acompressive stress to the NMOS region, and also may be used as asilicide protection layer when forming a metal silicide in the PMOSregion.

Referring to FIG. 1G, a second metal layer 134 is formed on the entirestructure, for example, on the first stress liner 124 in the NMOS regionand on the gate electrode 110 and the semiconductor substrate 100 in thePMOS region. The second metal layer 134 may be formed of the samematerial used to form the first metal layer 132 or formed of some othermaterial. The second metal layer 134 may include Ti, Co or Ni, mayfurther include Pt, V, or Sn. Also, the second metal layer 134 mayinclude Pt, Ir or Pd, and may further include Pt, V or Sn. The secondmetal layer 134 may be formed to have a thickness different from that ofthe first metal layer 132. Similar to the first metal layer 132, acapping layer (not shown) may be optionally formed on the second metallayer 134.

Referring to FIG. 1H, metal silicides 109 and 119 may be formed on thesource/drain region 106 and the gate electrode 110 in the PMOS regionthrough a silicidation reaction by performing a heat treatment processon the semiconductor substrate where the second metal layer 134 isformed. The heat treatment process may be performed under differentconditions from the heat treatment process for forming the metalsilicides 108 and 118 of the NMOS region. The metal silicides 109 and119 may be formed of TiSi₂, CoSi₂, NiSi, PtSi, Pt₂Si, IrSi or Pd₂Si. Themetal silicides 109 and 119 may include Pt, V or Sn. In the NMOS region,because the second metal layer 134 is formed on the first stress liner124, a metal silicide other than the previously formed metal silicides108 and 118 may not be formed.

Referring to FIG. 11, the second metal layer 134 remaining after thesilicidation reaction is performed may be removed. The first stressliner 124 may be exposed in the NMOS region, and the source/drain region106 and the gate electrode 110 where the metal silicides 109 and 119 areformed may be exposed in the PMOS region.

Referring to FIG. 1J, after a second stress liner 126 is formed on theentire structure, the portion of the second stress liner 126 in the NMOSregion may be removed, and only the portion of the second stress liner126 in the PMOS region remains. The second stress liner 126 may beformed to apply a tensile stress and be formed of SiCN, Si₃N₄, SiON,SiBN, SiO₂, SiC, SiC:H or SiCOH, similar to the first stress liner 124.The second stress liner 126 may be formed to have a thickness in therange of about 10 Å to about 1,000 Å. The second stress liner 126 mayincrease hole mobility in a P channel and drain current by applying atensile stress to the PMOS region. In example embodiments, a silicidemay be formed in the NMOS region first, and then a silicide may beformed in the PMOS region. However, example embodiments may not belimited thereto, and a silicide may be formed in the PMOS region first,and then a silicide may be formed in the NMOS region.

According to example embodiments, by applying both a dual silicideprocess and a dual stress liner process, an effect of each process canbe obtained. For example, metal silicides of an NMOS region and a PMOSregion may be formed of different materials, formed to have differentthicknesses, and formed under different conditions, so that resistanceRs of the NMOS region and the PMOS region may be controlled individuallyand equalized. By controlling a thickness of a silicide and a heattreatment process, excessive growth of a silicide in an edge portion ofan active region may be suppressed, and junction leakage may be reduced.Moreover, by suppressing excessive growth of silicide in boundaryregions of an active region and of a gate electrode, a difference ofresistance Rs generated according to the sizes of the active region andthe gate electrode may be minimized or reduced. Also, drain current maybe increased by individually increasing carrier mobility in the PMOSregion and the NMOS region by using a dual stress process.

By applying a dual stress liner as one of two silicide protection layersrequired when performing a dual silicide process, the manufacturingprocess may be simplified compared to a case where a dual silicideprocess and a stress liner process may be individually applied. Forexample, by simplifying one of the processes for forming a silicideprotection layer, a thin film process, a photolithography process, anetching process and/or a washing process may be omitted, therebysimplifying the manufacturing process and reducing manufacturing costsand time.

According to example embodiments, by simplifying one of the processesfor forming two silicide protection layers, both a dual silicide processand a dual stress liner process may be applied. Thus, in addition tosimplifying the process, the advantages of each process may be obtained.

While example embodiments have been particularly shown and describedwith reference to example embodiments thereof, it will be understood byone of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the following claims.

1. A method of fabricating a semiconductor device, comprising:sequentially siliciding and stressing a first MOS region; andsequentially siliciding and stressing a second MOS region aftersiliciding and stressing the first MOS region, the second MOS regionbeing a different type than the first MOS region, wherein thesequentially siliciding and stressing the first MOS region includesforming a silicide protection layer in the second MOS region, silicidingthe first MOS region and stressing the first MOS region.
 2. The methodof claim 1, wherein the silicide protection layer comprises SiCN, Si₃N₄,SiON, SiBN, SiO₂, SiC, SiC:H or SiCOH.
 3. The method of claim 1, whereinstressing the first MOS region includes forming a first stress linerover the first MOS region.
 4. The method of claim 3, wherein thesequentially siliciding and stressing the second MOS region includes:siliciding the second MOS region using the first stress liner to protectthe first MOS region from being silicided; and stressing the second MOSregion.
 5. The method of claim 1, wherein the first MOS region is anNMOS region, and the second MOS region is a PMOS region.
 6. The methodof claim 5, wherein stressing the first MOS region includes applying acompressive stress, and stressing the second MOS region includesapplying a tensile stress.
 7. The method of claim 1, wherein the firstMOS region is a PMOS region, and the second MOS region is an NMOSregion.
 8. The method of claim 7, wherein stressing the first MOS regionincludes applying a tensile stress, and stressing the second MOS regionincludes applying a compressive stress.
 9. A method of fabricating asemiconductor device, comprising: sequentially siliciding and stressinga first MOS region; and sequentially siliciding and stressing a secondMOS region after siliciding and stressing the first MOS region, thesecond MOS region being a different type than the first MOS region,wherein: the sequentially siliciding and stressing the first MOS regionincludes: exposing the first MOS region and forming a silicideprotection layer in the second MOS region, forming first metal silicideson a gate electrode and source/drain regions of the exposed first MOSregion and removing the silicide protection layer, and exposing thesecond MOS region and forming a first stress liner in the first MOSregion where the first metal silicides are formed; and the sequentiallysiliciding and stressing the second MOS region includes: forming secondmetal silicides on a gate electrode and a source/drain region of theexposed second MOS region, and forming a second stress liner in thesecond MOS region where the second metal silicides are formed.
 10. Themethod of claim 9, wherein each of the first stress liner and the secondstress liner comprises SiCN, Si₃N₄, SiON, SiBN, SiO₂, SiC, SiC:H orSiCOH.
 11. The method of claim 9, wherein each of the first stress linerand the second stress liner are formed to have a thickness in the rangeof about 10 Å to about 1,000 Å.
 12. The method of claim 9, wherein thegate electrode comprises conductive polysilicon.
 13. The method of claim9, wherein forming the first metal silicides comprises: forming a firstmetal layer on the semiconductor substrate and the gate electrode in thefirst MOS region, and on the silicide protection layer in the second MOSregion; forming the first metal silicides on the gate electrode and thesource/drain region of the first MOS region by performing a heattreatment process on the semiconductor substrate where the first metallayer is formed; and removing the first metal layer formed on thesilicide protection layer in the second MOS region.
 14. The method ofclaim 13, wherein the first metal layer comprises Ti, Co, Ni, V, Er, Zr,Hf, Mo or Yb.
 15. The method of claim 14, wherein the first metal layerfurther comprises Pt, V or Sn.
 16. The method of claim 9, whereinforming the second metal silicides comprises: forming a second metallayer on the first stress liner in the first MOS region and on thesemiconductor substrate and the gate electrode in the second MOS region;forming the second metal silicides on the gate electrode and thesource/drain region of the second MOS region by performing a heattreatment process on the semiconductor substrate where the second metallayer is formed; and removing the second metal layer formed on thesilicide protection layer in the first MOS region.
 17. The method ofclaim 16, wherein the second metal layer comprises Ti, Co, Ni, Pt, Ir orPd.
 18. The method of claim 17, wherein the second metal layer furthercomprises Pt, V or Sn.